As part of my course VLSI Systems and Architecture, I designed an SRAM with 256 different addresses, each of size 4 bits in Verilog. I then went on to design a Built -In Self Test Module (BIST) for the SRAM that can test 6 different patterns. The Built In Self Test (BIST) Module automatically runs any of the 6 algorithms based on the given input signal.

The BIST module can perform the following 6 BIST algorithms (1) Blanket Test 0 (2) Blanket Test 1 (3) CheckerBoard Test (4) Reverse CheckerBoard Test (5) March C Algorithm (6) March LR algorithm. 

Let me explain the design using the first Blanket Test 0 Algorithm. The BIST module starts  its execution, the moment Clock signal comes in. It stores “0000” in the address location ‘0’ of the SRAM. The address count of the BIST will thus increase after every clock cycle. The “0000”  is thus stored incrementally to each location of the SRAM. By the 255th clock cycle the BIST module would have stored(/written) “0000” to each location of the SRAM. The Write Enable signal is then turned to ‘0’ and starts reading from the SRAM. The reason for this is to make sure that “0000” has been correctly stored in the SRAM. 

Once the design for the BIST module  was developed in Verilog, it was then synthesized using 32 nm libraries from Synopsys in Design Compiler. These libraries generate a synthesized gate level netlist which can function at the speed of Giga Hertz. The netlists were ran at a clock of the period 3 nm., which is roughly 333 MHz. Any timing violations, such as setup time violation of hold time violation, if found, were then fixed using the PrimeTime tool. Schematic diagram of the implemented BIST module was then generated using the netlists with fixed timing constraints.