As part of our Advance Hardware Design course at the NYU  Tandon School of Engineering, we developed a 32-bit byte addressable MIPS based processor in VHDL that can execute any instruction in a single clock cycle.  While this processor function same as the original processor, it has an additional line from the control unit to support jump instructions. 

The PC value increases by 4 with every clock cycle. The Instruction Memory Module will accordingly send the instruction to the control module and the register file to decode. The register file then fetches the corresponding values for Rs and Rt. Both the values corresponding to Rs and Rt (or Sign extended immediate) will be the source A and Source B for the ALU. The ALU will accordingly process the signal. The result will be sent into Data memory where the value to be written back to the register will be decided by a mux.

We demonstrated this new design of the processor on a Basys-3 FPGA Board over its 7-Segment display and performed RC-5 Block Cipher with a self-written assembly code loaded to its memory. We implemented each individual block and then merged them to make one single cycle MIPS based processor. The basic concept used here is that if we add one binary number with the same value then we will get a zero at the end. Which is also equivalent to multiplying the number by 2. For instance, if we wanted to perform left rotate by 5, then we did left rotate by 1, 5 times. In order to test the working of the model on FPGA, we entered the RC 5 crypto algorithm in Assembly language and verified the output of FPGA with the intended results. Functional simulation and timing simulation tests along with its resource utilization were carried out for the project. The tests were carried out for both, the Left Rotate as well as Right Rotate. 

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