Cache Simulator

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For the course Computer System Architecture, I developed a Cache Simulator in C++ that would take memory addresses as its input and check its availability in L1 or L2 cache. The objective was to understand the functioning of the caches. The cache simulator takes several parameters of the cache such as block size, associativity, cache size, etc. along with a memory access trace file as its input program. The parameters were provided in a configuration file that in turn initializes variables for the L1 and L2 cache parameters. Memory would be allocated to the L1 and L2 caches, as per the parameters selected. Depending upon whether it is a Read Request or Write Request, the cache would output either as a Read Hit or Write Hit. In the case that the requested address is not available in the cache, L1 cache would pass on the request to L2 cache while L2 cache would fetch the address location from the main memory. L1 and L2 caches were Non-Inclusive and were equipped to deal with the scenarios Read Miss (Eviction using LRU policy), Write Hit and Write Miss.